By Monica S. Lam
This publication is a revision of my Ph. D. thesis dissertation submitted to Carnegie Mellon collage in 1987. It records the learn and result of the compiler know-how built for the Warp laptop. Warp is a systolic array equipped out of customized, high-performance processors, each one of that could execute as much as 10 million floating-point operations in keeping with moment (10 MFLOPS). below the path of H. T. Kung, the Warp laptop matured from a tutorial, experimental prototype to a advertisement manufactured from common electrical. The Warp laptop verified that the scalable structure of high-peiformance, programmable systolic arrays represents a realistic, competitively priced solu tion to the current and destiny computation-intensive functions. The luck of Warp ended in the follow-on iWarp venture, a joint undertaking with Intel, to enhance a single-chip 20 MFLOPS processor. the provision of the hugely built-in iWarp processor could have an important influence on parallel computing. one of many significant demanding situations within the improvement of Warp used to be to construct an optimizing compiler for the laptop. First, the processors within the xx A Systolic Array Optimizing Compiler array cooperate at a very good granularity of parallelism, interplay among processors needs to be thought of within the new release of code for person processors. moment, the person processors themselves derive their functionality from a VLIW (Very lengthy guide note) guide set and a excessive measure of inner pipelining and parallelism. The compiler comprises optimizations concerning the array point of parallelism, in addition to optimizations for the person VLIW processors.
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Additional info for A Systolic Array Optimizing Compiler
As shown in the figure, the second cell cannot start its computation until the first result is deposited into the Y queue. However, once a cell starts, it will not stall again, because of the equal and constant input and output rates of each cell. Therefore, the throughput of the array is one polynomial evaluation every eight clocks. However, the hardware is capable of delivering a throughput of one result every clock. This maximum throughput can be achieved as follows: We notice that the semantics of the computation remains unchanged if we reorder communication operations on different queue buffers.
Control path. Each Warp cell has its own local program memory and sequencer. Even if the cells execute the same program, it is not easy to broadcast the microinstruction words to all the cells, or to propagate them from cell to cell, since the instructions are very wide. Moreover, although the cell programs may be the same, cells often do not execute them in lock step. The local sequencer also supports conditional branching efficiently. In SIMD machines, branching is achieved by masking. The execution time is equivalent to the swn of the execution time of both branches.
Since no data is removed from the X queue until there is data on the Y queue, the X queue must be able to buffer up the seven data items. Otherwise, a deadlock situation would occur with the first cell blocked trying to send to a full X queue and the second cell blocked waiting for data on the empty Y queue. Therefore, relaxing the sequencing constraints between two queues has the effect of increasing the throughput of the system, at the expense of increasing the buffer space requirement along the communication links.