By Johan Huijsing, Michiel Steyaert, Arthur H.M. van Roermund
This 10th quantity of Analog Circuit layout concentrates on three themes: 1. Scalable Analog Circuits, 2. High-Speed D/A Converters, and three. RF strength Amplifiers. every one subject is roofed by means of 6 papers, written by way of the world over well-known specialists on that subject. those papers have an instructional nature geared toward enhancing the layout of analog circuits. The ebook is split into 3 components: half I, Scalable Analog Circuit layout describes in 6 papers problems with: scalable high-speed layout, scalable high-resolution mixed-mode ADC and OpAmp layout, scalable high-voltage layout for XDSL, scalability of wire-line entrance ends, reusable IP analog layout, and porting CAD analog layout. half II, High-Speed D/A Converters describes in 6 papers problems with: creation to high-speed D/A converter layout, retargetable 12-bit 200-MHz CMOS present guidance layout, high-speed CMOS D/A converters for upstream cable purposes, static and dynamic functionality barriers, the linearity problem of D/A converters for communications, and a 400-MHz, 10-bit charge-domain CMOS D/A converter for low-spurious frequency synthesis. half III, RF energy Amplifiers describes in 6 papers problems with: approach features, review and trade-offs, linear transmitter architectures, GaAs microwave SSPAs, Monolithic transformer-coupling in Si-bipolar, and RF strength amplifier layout in CMOS.
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Additional resources for Analog Circuit Design: Scalable Analog Circuit Design, High-Speed D A Converters, RF Power Amplifiers
A total of 4-5 orders of noise shaping: fewer than 4 is undoubtedly “leaving potential performance on the table” while greater than 5 orders probably buys little improvement a total of some 4-8 bits of quantization: a few bits of quantization bring significant improvements, perhaps particularly in loop 33 stability characteristics, but circuit complexity increases rather nonlinearly with too many bits two or maybe three cascaded loops; (although, a single noiseshaped loop could also be a well optimised solution, as multi-bit quantization eases the loop stability criteria and permits very aggressive higher order noise shaping) at least 2 orders of noise shaping and 2-3 bits of quantization in the first loop, to ease the required accuracy of the amplifier which copies the quantization noise into the second loop the remaining bits of quantization spread as much as possible and probably not bit-shuffled bit-shuffling of the first loop multi-bit quantizer of course possibly dither in the first loop.
Others favour perhaps one redundant bit per 4 bits; this latter still allows large errors but only increases the number of bit trials by 5/4. A conceptually elegant alternative which achieves the same result is a successive approximation with an array with slightly less than binary weighting, as in Fig 2c. It will be apparent from inspection that this also allows a search path which converges on the correct result despite moderate errors on the way. However, it suffers the major disadvantage of using non-binary-weighted elements.
To achieve >12 bits performance various of these capacitors are trimmed by further small arrays of capacitors which are switched in or out at test [1,2] (Fig 1). The capacitors are usually double plates of polysilicon with silicon dioxide dielectric which are very mechanically and electrically stable. Since these structures are very stable post-manufacturing, the trim is usually once-only with a small on-chip PROM, often comprising electrically-blown polysilicon fuses. This architecture is relatively cheap to manufacture and easy to use in the end application as no 27 calibration cycles are needed.